Adapting Hardware Systems by Means of Multi-Objective Evolution

Adapting Hardware Systems by Means of Multi-Objective Evolution

  • Paul Kaufmann
Publisher:Logos Verlag Berlin GmbHISBN 13: 9783832535308ISBN 10: 3832535306

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Adapting Hardware Systems by Means of Multi-Objective Evolution is written by Paul Kaufmann and published by Logos Verlag Berlin GmbH. It's available with International Standard Book Number or ISBN identification 3832535306 (ISBN 10) and 9783832535308 (ISBN 13).

Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as "Evolvable Hardware" (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering. In this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes. Focusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.