Cache and Memory Hierarchy Design

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Cache and Memory Hierarchy Design is written by Steven A. Przybylski and published by Elsevier. It's available with International Standard Book Number or ISBN identification 0080500595 (ISBN 10) and 9780080500591 (ISBN 13).

An authoritative book for hardware and software designers. Caches are by far the simplest and most effective mechanism for improving computer performance. This innovative book exposes the characteristics of performance-optimal single and multi-level cache hierarchies by approaching the cache design process through the novel perspective of minimizing execution times. It presents useful data on the relative performance of a wide spectrum of machines and offers empirical and analytical evaluations of the underlying phenomena. This book will help computer professionals appreciate the impact of caches and enable designers to maximize performance given particular implementation constraints.